Job Code : AAI01-1045

Location - Bangalore

Experience - 4 to 8 Years

Take complete ownership for implementation of Block level designs

Responsible for planning and execution of all aspects of Physical Design including Synthesis, Floor planning, Place and Route, Clock Tree Synthesis, Clock Distribution, IP integration, Extraction, Timing closure, Power and Signal Integrity Analysis, Physical Verification, DFM and Tape Out on 16nm nodes or below

Must have participated in all stages of the design (floor planning, placement, CTS, routing, crosstalk avoidance, physical verification, IREM)

Well versed with the Level timing closure (STA), Timing closure methodologies

Role involves tasks in estimating power using industry standard tool,designing power grid , analyze power grid, doing static IR drop, dynamic IR drop

Role involves analyzing DRC, LVS,ERC rule files for industry standard layout verification

Working on very leading technology nodes: 16nm, 14nm, 10nm, 7nm

Well aware of place and route methodologies and hands on experience with timing convergence

Good communication skill to negotiate with top level for convergence

Job Code : AAI02-1001

Location - Bangalore

Experience - 4+ Years

Take complete ownership for implementation of Block level designs

DFT logic integration and verification

Experience on debugging low coverage

Gate Level DFT verification with and without timing

Pattern generation, verification and delivery to ATE team

· Post silicon debug and support on failing patterns · Experience of leading a small DFT team is a plus · Good experience on EDA tools of reputed vendors like Mentor, Synopsys · LBIST experience is plus · DFT mode STA and timing closer support · Familiar to Verilog and RTL simulation

Job Code : AAI03-1001

Location - Bangalore

Experience - 3 to 15 Years

Job Description

Self-starter with 3+ years of relevant experience on IP / Sub-system verification on multi millionGate and complex Design with multiple clocks with minimal supervision. Hands-on knowledge with strong fundamentals of SV/ UVM (and Verilog) and ability to modify or develop checkers, monitors etc. from scratch.

Must Have

Ability to debug Test bench and RTL issues and handle legacy Testbench and make enhancements. Highly desirable experience in IP with system interface protocols like AMBA /AHB or AXI. Must have experience in end to end IP verification project cycle, including TestbenchStrategies, TB development, simulation debugging.

Job Code : AAI03-1001

Location - Bangalore

Qualification - Bachelor in Computer Science

Experience - 2 to 4 years of experience

Job Description

Understanding the end user s requirement and translating the requirement into a business requirement document for the Chatbot development or implementation. Developing chatbot queries and responses model based on the uses input in the form of chatbot consumable format. Create NLP modules to enhance the chatbot development process and improve the accuracy of the Chatbot. Developing and fine - tuning machine learning algorithm to improve chatbot engine accuracy and speed. Creation of test plan, test cases and testing chatbot responses using various tools such as selenium.

Must Have

Proficient in using python 3.x platform. o Have worked on chatbot development or implementation in a real business scenario. o Proficiency in Natural Language processing packages such as NLTK, Spacy, Gensim etc. o Pro - efficient in Deep Learning algorithm using Keras, Pytorch etc o Knowledge of Social platforms (Facebook, Twitter, LinkedIn, Google, WhatsApp etc.) and their APIs preferred. o Hand - on knowledge of Database, Excel, Powerpoint

Desired Skill

Working knowledge of HTML, JavaScript o Worked on chatbot platform such as Alexa, Watson, Luis, Rasa o Must have experience working with unstructured data related to text, voice, video and image analytics.